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cy62256n 256k (32k x 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06511 rev. *b revised june 03, 2009 features temperature ranges ? commercial: 0c to 70c ? industrial: ?40c to 85c ? automotive-a: ?40c to 85c ? automotive-e: ?40c to 125c high speed: 55 ns voltage range: 4.5v to 5.5v operation low active power ? 275 mw (max) low standby power (ll version) ? 82.5 w (max) easy memory expansion with ce and oe features ttl-compatible inputs and outputs automatic power down when deselected cmos for optimum speed and power available in pb-free and non pb-free 28-pin (600-mil) pdip, 28-pin (300-mil) narrow soic, 28-pin tsop-i, and 28-pin reverse tsop-i packages functional description the cy62256n [1] is a high performance cmos static ram organized as 32k words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ) and active low output enable (oe ) and tristate driver s. this device has an automatic power down feature, reducing the power consumption by 99.9 percent when deselected. an active low write enable signal (we ) controls the writing/reading operation of the memory. when ce and we inputs are both low, data on the eight data input/output pins (i/o 0 through i/o 7 ) is written into the memory location addressed by the address present on the address pins (a 0 through a 14 ). reading the device is accomplished by selecting the device and enabling the outputs, ce and oe active low, while we remains inactive or high. under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. the input/output pins remain in a high impedance state unless the chip is selected, outputs are enabled, and write enable (we ) is high. note 1. for best practice recommendations, do refer to the cypress application note ?system design guidelines? on http://www.cypress. com a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 column decoder row decoder sense amps inputbuffer power down we oe i/o 0 ce i/o 1 i/o 2 i/o 3 32k x 8 arra y i/o 7 i/o 6 i/o 5 i/o 4 a 10 a 13 a 11 a 12 a a 14 a 1 0 logic block diagram [+] feedback
cy62256n document #: 001-06511 rev. *b page 2 of 14 pin configurations figure 1. 28-pin dip and narrow soic figure 2. 28-pin tsop i and reverse tsop i product portfolio product v cc range (v) speed (ns) power dissipation operating, i cc (ma) standby, i sb2 ( a) min typ [2] max typ [2] max typ [2] max cy62256nl commercial / industrial 4.5 5.0 5.5 70 25 50 2 50 cy62256nll commercial 70 25 50 0.1 5 cy62256nll industrial 55/70 25 50 0.1 10 cy62256nll automotive-a 55/70 25 50 0.1 10 cy62256nll automotive-e 55 25 50 0.1 15 table 1. pin definitions pin number type description 1?10, 21, 23?26 input a 0 ?a 14 . address inputs 11?13, 15?19, input/output i/o 0 ?i/o 7 . data lines. used as input or output lines depending on operation 27 input/control we . when selected low, a write is conducted. when selected high, a read is conducted 20 input/control ce . when low, selects the chip. when high, deselects the chip 22 input/control oe . output enable. controls th e direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are tristated, and act as input data pins 14 ground gnd . ground for the device 28 power supply v cc . power supply for the device note 2. typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (t a = 25c, v cc ). parameters are guaranteed by design and characterization, and not 100% tested. [+] feedback
cy62256n document #: 001-06511 rev. *b page 3 of 14 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied ............................................. -55 c to +125 c supply voltage to ground potential (pin 28 to pin 14)............................................?0.5v to +7.0v dc voltage applied to outputs in high-z state [3] .................................... ?0.5v to v cc + 0.5v dc input voltage [3] ................................ ?0.5v to v cc + 0.5v output current into outputs (low)............................. 20 ma static discharge voltage....... ........... ............ ............ > 2001v (per mil-std-883, method 3015) latch up current.................................................... > 200 ma operating range range ambient temperature (t a ) [4] v cc commercial 0 c to +70 c 5v 10% industrial ?40 c to +85 c 5v 10% automotive-a ?40 c to +85 c 5v 10% automotive-e ?40 c to +125 c 5v 10% electrical characteristics over the operating range parameter description test conditions -55 -70 unit min typ [2] max min typ [2] max v oh output high voltage v cc = min., i oh = ? 1.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 2.1 ma 0.4 0.4 v v ih input high voltage 2.2 v cc +0.5v 2.2 v cc +0.5v v v il input low voltage ?0.5 0.8 ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?0.5 +0.5 ?0.5 +0.5 a i oz output leakage current gnd < v o < v cc , output disabled ?0.5 +0.5 ?0.5 +0.5 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc l-commercial/ industrial 25 50 ma ll-commercial 25 50 ma ll - industrial 25 50 25 50 ma ll - auto-a 25 50 25 50 ma ll - auto-e 25 50 ma i sb1 automatic ce power down current? ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max l0.40.6ma ll-commercial 0.3 0.5 ma ll - industrial 0.3 0.5 0.3 0.5 ma ll - auto-a 0.3 0.5 0.3 0.5 ma ll - auto-e 0.3 0.5 ma i sb2 automatic ce power down current? cmos inputs max. v cc , ce > v cc ? 0.3v v in > v cc ? 0.3v, or v in < 0.3v, f = 0 l250 a ll-commercial 0.1 5 a ll - industrial 0.1 10 0.1 10 a ll - auto-a 0.1 10 0.1 10 a ll - auto-e 0.1 15 a capacitance parameter description test conditions [5] max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 6pf c out output capacitance 8 pf notes 3. v il (min.) = ? 2.0v for pulse durations of less than 20 ns. 4. t a is the ?instant-on? case temperature. 5. tested initially and after any design or process changes that may affect these parameters. [+] feedback
cy62256n document #: 001-06511 rev. *b page 4 of 14 thermal resistance parameter description [5] test conditions dip soic tsop rtsop unit ja thermal resistance (junction to ambient) still air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board 75.61 76.56 93.89 93.89 c/w jc thermal resistance (junction to case) 43.12 36.07 24.64 24.64 c/w figure 3. ac test loads and waveforms data retention characteristics parameter description conditions [6] min typ [2] max unit v dr v cc for data retention 2.0 v i ccdr data retention current l v cc = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v 250 a ll-commercial 0.1 5 a ll - industrial/auto-a 0.1 10 a ll - auto-e 0.1 10 a t cdr [8] chip deselect to data retention time 0 ns t r [8] operation recovery time t rc ns 3.0v 5v output r1 1800 r2 990 100 pf including jig and scope gnd 90% 10% 90% 10% <5ns <5 ns 5v output r1 1800 r2 990 5pf including jig and scope (a) (b) output 1.77v equivalent to: th venin equivalent all input pulses 639 note 6. no input may exceed v cc + 0.5v. figure 4. data retention waveform 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc [+] feedback
cy62256n document #: 001-06511 rev. *b page 5 of 14 switching characteristics over the operating range [7] parameter description cy62256n-55 cy62256n-70 unit min max min max read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 5 5 ns t ace ce low to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low-z [8] 55ns t hzoe oe high to high-z [8, 9] 20 25 ns t lzce ce low to low-z [8] 55ns t hzce ce high to high-z [8, 9] 20 25 ns t pu ce low to power up 0 0 ns t pd ce high to power down 55 70 ns write cycle [10, 11] t wc write cycle time 55 70 ns t sce ce low to write end 45 60 ns t aw address setup to write end 45 60 ns t ha address hold from write end 0 0 ns t sa address setup to write start 0 0 ns t pwe we pulse width 40 50 ns t sd data setup to write end 25 30 ns t hd data hold from write end 0 0 ns t hzwe we low to high-z [8, 9] 20 25 ns t lzwe we high to low-z [8] 55ns switching waveforms figure 5. read cycle no. 1 [12, 13] notes 7. test conditions assume signal transition time of 5 ns or less , timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 100-pf load capacitance. 8. at any temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 9. t hzoe , t hzce , and t hzwe are specified with c l = 5 pf as in (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 10. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold ti ming should be referenced to the rising edge of the signal tha t terminates the write. 11. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd . 12. device is contin uously selected. oe , ce = v il . 13. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha [+] feedback
cy62256n document #: 001-06511 rev. *b page 6 of 14 figure 6. read cycle no. 2 [13, 14] figure 7. write cycle no. 1 (we controlled) [10, 15, 16] figure 8. write cycle no. 2 (ce controlled) [10, 15, 16] notes 14. address valid prior to or coincident with ce transition low. 15. data i/o is high impedance if oe = v ih . 16. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 17. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu data out high impedance impedance icc isb t hzoe t hzce t pd oe ce high v cc supply current t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in valid note 17 t wc t aw t sa t ha t hd t sd t sce we data i/o address ce data in valid [+] feedback
cy62256n document #: 001-06511 rev. *b page 7 of 14 figure 9. write cycle no. 3 (we controlled, oe low) [11, 16] switching waveforms (continued) data i/o address t hd t sd t lzwe t sa t ha t aw t wc ce we t hzwe data in valid note 17 [+] feedback
cy62256n document #: 001-06511 rev. *b page 8 of 14 typical dc and ac characteristics 1.2 1.4 1.0 0.6 0.4 0.2 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 0.8 ? 55 25 125 ? 55 25 125 1.2 1.0 0.8 normalized t aa 120 100 80 60 40 20 0.0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage ambient temperature ( c) vs. ambient temperature ambient temperature ( c) output voltage (v) output source current 0.0 0.8 1.4 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t aa supply voltage (v) normalized access time 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs. output voltage 0.6 0.4 0.2 0.0 normalized i cc normalized i cc , i sb i cc i cc i sb 0.6 0.8 0 1.3 1.2 v in = 5.0v t a = 25 c 1.4 ? 55 25 105 2.5 2.0 1.5 ambient temperature ( c) 1.0 0.5 0.0 ?0.5 i sb 3.0 standby current i sb2 a normalized supply current vs. ambient temperature v in = 5.0v v cc = 5.0v v cc = 5.0v v in = 5.0v vs. supply voltage normalized access time vs. ambient temperature t a = 25 c v cc = 5.0v t a = 25 c v cc = 5.0v vs. output voltage v cc = 5.0v t a = 25 c [+] feedback
cy62256n document #: 001-06511 rev. *b page 9 of 14 typical dc and ac characteristics (continued) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 4.0 normalized i po supply voltage (v) typical power-on current vs. supply voltage 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 1.25 1.00 0.75 10 20 30 40 normalized i cc cycle frequency (mhz) 0.0 5.0 0.0 1000 0.50 normalized i cc vs. cycle time t a = 25 c v cc = 5.0v v in = 5.0v t a = 25 c v cc = 4.5v truth table ce we oe inputs/outputs mode power h x x high-z deselect/power down standby (i sb ) l h l data out read active (i cc ) l l x data in write active (i cc ) l h h high-z output disabled active (i cc ) [+] feedback
cy62256n document #: 001-06511 rev. *b page 10 of 14 ordering information speed (ns) ordering code package diagram package type operating range 55 cy62256nll ? 55sni 51-85092 28-pin (300-mil) narrow soic industrial cy62256nll ? 55snxi 28-pin (300-mil) narrow soic (pb-free) cy62256nll ? 55zi 51-85071 28-pin tsop i cy62256nll ? 55zxi 28-pin tsop i (pb-free) cy62256nll ? 55zxa 51-85071 28-pin tsop i (pb-free) automotive-a cy62256nll ? 55snxe 51-85092 28-pin (300-mil) narrow soic (pb-free) automotive-e cy62256nll ? 55zxe 51-85071 28-pin tsop i (pb-free) cy62256nll ? 55zrxe 51-85074 28-pin reverse tsop i (pb-free) 70 cy62256nl ? 70pc 51-85017 28-pin (600-mil) molded dip commercial cy62256nl ? 70pxc 28-pin (600-mil) molded dip (pb-free) cy62256nll ? 70pc 28-pin (600-mil) molded dip cy62256nll ? 70pxc 28-pin (600-mil) molded dip (pb-free) cy62256nl ? 70snc 51-85092 28-pin (300-mil) narrow soic cy62256nl ? 70snxc 28-pin (300-mil) narrow soic (pb-free) cy62256nll ? 70snc 28-pin (300-mil) narrow soic cy62256nll ? 70snxc 28-pin (300-mil) narrow soic (pb-free) cy62256nll ? 70zc 51-85071 28-pin tsop i cy62256nll ? 70zxc 28-pin tsop i (pb-free) cy62256nl?70sni 51-85092 28-pin (300-mil) narrow soic industrial cy62256nl?70snxi 28-pin (300-mil) narrow soic (pb-free) cy62256nll ? 70sni 28-pin (300-mil) narrow soic cy62256nll ? 70snxi 28-pin (300-mil) narrow soic (pb-free) cy62256nll ? 70zi 51-85071 28-pin tsop i cy62256nll ? 70zxi 28-pin tsop i (pb-free) cy62256nll ? 70zri 51-85074 28-pin reverse tsop i cy62256nll ? 70zrxi 28-pin reverse tsop i (pb-free) cy62256nll ? 70snxa 51-85092 28-pin (300-mil) narrow soic (pb-free) automotive-a do contact your local cypress sales repres entative for availability of these parts [+] feedback
cy62256n document #: 001-06511 rev. *b page 11 of 14 package diagrams figure 10. 28-pin (600-mil) molded dip (51-85017) figure 11. 28-pin (300-mil) snc (narrow body) (51-85092) 51-85017-*c 51-85092-*b [+] feedback
cy62256n document #: 001-06511 rev. *b page 12 of 14 figure 12. 28-pin tsop i (8 x 13.4 mm) (51-85071) 51-85071-*g [+] feedback
cy62256n document #: 001-06511 rev. *b page 13 of 14 figure 13. 28-pin tsop i (8 x 13.4 mm) (51-85074) 51-85074-*f [+] feedback
document #: 001-06511 rev. *b revised june 03, 2009 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. cy62256n ? cypress semiconductor corporation, 2006-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com document title: cy62256n 256k (32k x 8) static ram document number: 001- 06511 rev. ecn no. submission date orig. of change description of change ** 426504 see ecn nxr new data sheet *a 488954 see ecn nxr added automotive product updated ordering information table *b 2715270 06/05/20 09 vkn/aesa updated pod of 28-pin (600-m il) molded dip pack age (spec# 51-85017) [+] feedback

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